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IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O
FEATURES:
- - - - - - - - - Typical tSK(0) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP and 0.40mm pitch TVSOP packages Extended commercial range of -40C to +85C VCC = 3.3V 0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range CMOS power levels (0.4 W typ. static) All inputs, outputs and I/O are 5 Volt tolerant Supports hot insertion
IDT74LVC16646A
DESCRIPTION:
The LVC16646A 16-bit bus transceiver/register is built using advanced dual metal CMOS technology. This high-speed, low power device is organized as two independent 8-bit D-type transceivers with 3-state D-type registers. The control circuitry is organized for multiplexed transmission of data between the A bus and B bus either directly or from the internal storage registers. Each 8-bit transceiver/register features direction control (DIR), over-riding Output Enable control (OE) and Select lines (SAB and SBA) to select either real-time data or stored data. Separate clock inputs are provided for A and B port registers. Data on the A or B data bus, or both, can be stored in the internal registers by the low-to-high transitions at the appropriate clock pins. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. All pins can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVC16646A has been designed with a 24mA output driver. The driver is capable of driving a moderate to heavy load while maintaining speed performance.
Drive Features for LVC16646A: - High Output Drivers: 24mA - Reduced system switching noise
APPLICATIONS:
* 5V and 3.3V mixed voltage systems * Data communication and telecommunication systems
Functional Block Diagram
56
29
1OE
2OE
1DIR
1
28
2DIR
55
1C LKBA 1SBA
2C LKBA 2S BA 2C LKAB
30
54 2
31 27
1C LKAB 1SAB
3
26
2SAB
B REG 1D C1
5
B REG 1D C1
52
1A1
A REG 1D C1
1B1
2A1
15
A REG 1D C1
42
2B1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
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c 1998 Integrated Device Technology, Inc.
APRIL 1999
DSC-4488/1
IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM(2) VTERM(3) TSTG IOUT IIK IOK ICC ISS Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND
(1)
Unit V V C mA mA mA
LVC Link
Max. - 0.5 to +6.5 - 0.5 to +6.5 - 65 to +150 - 50 to +50 - 50 100
1DIR 1CLKAB
1S AB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SO56-1 SO56-2 SO56-3
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OE 1CLKBA
1S BA
GND
1A1 1A 2
GND
1B1 1B 2
VCC
1A3 1A4 1A 5
VCC
1B 3 1B 4 1B 5
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
GND
1A6 1A 7 1A 8 2A1 2A 2 2A3
GND
1B6 1B 7 1B 8 2B 1
CAPACITANCE (TA = +25OC, f = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 4.5 6.5 6.5 Max. 6 8 8 Unit pF pF pF
LVC Link
2B 2 2B 3
CI/O
GND
2A 4 2A5 2A 6
GND
2B 4 2B 5 2B 6
NOTE: 1. As applicable to the device type.
VCC
2A7 2A8
VCC
2B 7 2B8
PIN DESCRIPTION
Pin Names xAx xBx xCLKAB, xCLKBA xSAB, xSBA xOE xDIR Description Data Register A Inputs Data Register B 3-State Outputs Data Register B Inputs Data Register A 3-State Outputs Clock Pulse Inputs Output Data Source Select Inputs Output Enable Inputs Direction Control Inputs
GND
2SA B 2C LKAB 2D IR
GND
2SBA 2C LKBA 2OE
SSOP/ TSSOP/ TVSOP TOP VIEW
c 1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
EXTENDED COMMERCIAL TEMPERATURE RANGE
FUNCTION TABLE
xOE X X H H L L L L xDIR X X X X L L H H xCLKAB X H or L X X X H or L
(1)
Data I/O(2) xSAB X X X X X X L H xSBA X X X X L H X X xAx Input Unspecified(2) Input Input Output Output Input Input xBx Unspecified(2) Input Input Input Input Input Output Output Operation or Function Store A, B unspecified(2) Store B, A unspecified(2) Store A and B Data Isolation, hold storage Real Time B Data to A Bus Stored B Data to A Bus Real Time A Data to B Bus Stored A Data to B Bus
Inputs xCLKBA X H or L X H or L X X
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW-to-HIGH Transition 2. The data output functions may be enabled or disabled by various signals at the xOE or xDIR inputs. Data input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40OC to +85OC
Symbol VIH VIL IIH IIL IOZH IOZL IOFF VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input Leakage Current High Impedance Output Current (3-State Output pins) Input/Output Power Off Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 0V, VIN or VO 5.5V VCC = 2.3V, IIN = - 18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC 3.6 VIN 5.5V(2) Quiescent Power Supply Current Variation One input at VCC - 0.6V other inputs at VCC or GND -- -- -- -- -- -- -- - 0.7 100 -- -- -- 50 - 1.2 -- 10 10 500 A
LVC Link
Test Conditions VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VI = 0 to 5.5V VO = 0 to 5.5V
Min. 1.7 2 -- -- -- --
Typ.(1) -- -- -- -- -- --
Max. -- -- 0.7 0.8 5 10
Unit V V A A A V mV A
NOTES: 1. Typical values are at VCC = 3.3V, +25C ambient. 2. This applies in the disabled state only.
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IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
EXTENDED COMMERCIAL TEMPERATURE RANGE
BUS A
BUS B
BUS A
BUS B
xDIR L
xOE L
xCLKAB X
xCLKBA X
xSAB X
xSBA L
xDIR H
xOE L
xCLKAB X
xCLKBA X
xSAB L
xSBA X
REAL-TIME TRANSFER BUS B TO A
REAL-TIME TRANSFER BUS A TO B
BUS A
BUS B
BUS A
BUS B
xDIR X X X
xOE X X H
xCLKAB
xCLKBA X

X
xSAB X X X
xSBA X X X
xDIR L H
(1)
xOE L L
xCLKAB X H or L
xCLKBA H or L X
xSAB X H
xSBA H X
STORAGE FROM A, B, OR A AND B
TRANSFER STORED DATA TO A AND/OR B
NOTE: 1. Cannot transfer data to A Bus and B Bus simultaneously.
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IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3.0V VCC = 3.0V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3.0V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) IOH = - 0.1mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2.2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55
LVC Link
Unit V
V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to +85C.
OPERATING CHARACTERISTICS, VCC = 3.3V 0.3V, TA = 25C
Symbol CPD CPD Parameter Power Dissipation Capacitance per Transceiver Outputs enabled Power Dissipation Capacitance per Transceiver Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 60 12 Unit pF pF
5
IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
EXTENDED COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS (1)
VCC = 2.7V Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tSU tH tW tSK(o) Parameter Propagation Delay xAx to xBx or xBx to xAx Propagation Delay CLKBA to xAx or CLKAB to xBx Propagation Delay xSBA or xSAB to xAx or xBx Output Enable Time xOE to xAx or xBx Output Enable Time xDIR to xAx or xBx Output Disable Time xOE to xAx or xBx Output Disable Time xDIR to xAx or xBx Set-up Time HIGH or LOW xAx or xBx before CLKAB or CLKBA Hold Time HIGH or LOW xAx or xBx after CLKAB or CLKBA Clock Pulse Width HIGH or LOW Output Skew(2) Min. 150 -- -- -- -- -- -- -- 3.2 -- 3.3 -- Max. -- 6.8 7.9 9.2 8.5 8.5 7.7 7.8 -- -- -- -- VCC = 3.3V0.3V Min. 150 1.3 1.8 1.7 1.3 1.4 2.1 2 2.9 0.3 3.3 -- Max. -- 5.7 6.7 7.7 6.9 7.2 6.9 7 -- -- -- 500 Unit MHz ns ns ns ns ns ns ns ns ns ns ps
NOTES: 1. See test circuits and waveforms. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction.
6
IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS: TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V 0.3V 6 2.7 1.5 300 300 50 VCC(1) = 2.7V 6 2.7 1.5 300 300 50 VCC(2)= 2.5V 0.2V Unit 2 x Vcc V Vcc VCC / 2 150 150 30 V V mV mV pF
LVC Link
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
LVC Link
TEST CIRCUITS FOR ALL OUTPUTS
VCC 500 Pulse (1, 2) Generator VIN D.U.T. 500 CL VOUT VLOAD Open GND
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT SW ITCH NORMALLY CLOSED LOW tPZH OUTPUT SW ITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VOL+VLZ VOL VOH VOH-VHZ 0V
RT
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
LVC Link
NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
LVC Link NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Switch VLOAD
SET-UP, HOLD, AND RELEASE TIMES
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL
LVC Link
tSU
tH
GND Open
tREM
OUTPUT SKEW - tsk (x)
VIH INPUT VT 0V VOH OUTPUT 1 VT VOL VOH OUTPUT 2 tPLH2 tPHL2 VT VOL
SYNCHRONOUS CONTROL
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
LVC Link
tPLH1
tPHL1
PULSE WIDTH
LOW -HIGH-LOW PULSE tW HIGH-LOW -HIGH PULSE VT
LVC Link
VT
tSK (x)
tSK (x)
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. Link
7
IDT74LVC16646A 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
EXTENDED COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX LVC X Bus-Hold XX Family XXXX Device Type XX Package Temp. R ange
PV PA PF 646A 16 Blank 74
Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) 16-Bit Bus Transceiver/R egister Double-D ensity with Resistors, 24m A No Bus-hold -40C to +85C
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